Enabling large feature alignment marks with sidewall image transfer patterning

ABSTRACT

In an embodiment, this disclosure relates to a method of creating an alignment feature within a sidewall image transfer process by the addition of a block mask. The presence of the alignment feature would enable better overlay and alignment for subsequent lithographic stacks.

DOMESTIC PRIORITY

This application is a divisional of U.S. patent application Ser. No. 14/972,915, filed Dec. 17, 2015, the disclosure of which is incorporated by reference herein in its entirety.

BACKGROUND

The present disclosure relates to a method of enabling large feature alignment marks with sidewall image transfer patterning.

Semiconductor manufacturing utilizes the sequential patterning of process layers on a single semiconductor wafer. Lithographic exposure tools known as steppers or scanners print multiple integrated circuit patterns or fields (also known as product cells) by lithographic methods on successive layers of the wafer. These exposure tools transfer patterns of a photo mask having customized circuit patterns to thin films formed on a wafer. In doing so, different layers are patterned by applying step and repeat lithographic exposure or step and scan lithographic exposure, in which the full area of the wafer is patterned by sequential exposure of the stepper fields containing one or more integrated circuits.

The image transfer process comprises steps of forming a photoresist layer on a non-process layer, illuminating the photoresist layer through a photo mask having the customized circuit patterns, developing the photoresist layer and then etching the non-process layer by using the patterned photoresist layer as a mask to accomplish the image transfer process. This image transfer process is performed several times to transfer the circuit patterns to each non-process layer to form the integrated circuit device. Typically, 20 to 50 layers are required to create an integrated circuit.

In order to match corresponding features in successive lithographic process layers on the semiconductor wafer, it is important to keep both alignment and overlay errors as small as possible and within predetermined limits. Measurements are typically performed using metrology imaging tools, such as optical, scanning e-beam or atomic force microscopy systems. In practice, alignment and overlay metrology systems often require different specialized target designs and locations on each layer.

Overlay targets can be comprised of sub-patterns from both the same and different masks. The images are analyzed to determine the relative layer-to-layer and within-layer placement of the sub-patterns among the various mask layers printed on the wafer. Overlay error is the deviation of the relative position among patterns from their designed relative positions, as determined by an overlay metrology tool. In doing so, the overlay correlation set in an exposure tool is used to insure alignment precision between the successively patterned layers. A metrology process determines precision of the overlay alignment by referring to the overlay alignment mark sets of the successive patterned layers.

To ensure circuit functionality, overlay errors must be minimized among all wafer patterns, consistent with the ground rules of the most critical circuit devices. While prior art has focused on several metrology processes for determining overlay alignment, as semiconductor device critical dimensions continue to shrink, and the speed and functionality requirements thereof continue to increase, improvements continue to be needed in minimizing alignment and overlay errors.

That is, a need exists in the art for methods, apparatus, and structures that align successively patterned layers to reduce misalignment errors as critical dimensions of semiconductor devices continue to shrink and the processing requirements thereof continue to develop.

SUMMARY

According to an embodiment of the present invention, a method of forming an alignment feature and a sidewall feature on an integrated circuit component comprises depositing a spacer material layer on the integrated circuit component comprising a gate electrode layer and a hard mask layer on the gate electrode layer; depositing a first mask layer on the spacer material layer and patterning an opening in the first mask layer; wherein the first mask layer is located on the alignment portion of the spacer material layer; removing the spacer material layer located in the opening of the first mask layer; depositing a mandrel material layer after removing the spacer material layer and polishing the mandrel material layer to form a polished mandrel material layer; depositing a second mask layer on the polished mandrel material layer and patterning a second opening in the second mask layer to expose an unprotected area of the polished mandrel material layer; removing the polished mandrel material layer located in the unprotected area to form a mandrel; depositing a sidewall spacer layer on the mandrel comprising a remaining mandrel material layer; etching the remaining mandrel material layer; and removing the alignment portion of the spacer material to form the alignment feature and forming the sidewall features in the hard mask layer.

According to another embodiment, a method of forming an alignment feature and a sidewall feature on an integrated circuit component comprises depositing a spacer material layer on the integrated circuit component comprising a gate electrode layer; a silicon nitride layer located on top of the gate electrode layer, a silicon dioxide layer located on top of the silicon nitride layer, and a hard mask planarization layer located on top of the silicon dioxide layer; depositing a first photoresist layer on the spacer material layer and patterning an opening in the first photoresist layer; wherein the first photoresist layer is located on the alignment portion of the spacer material layer; removing the spacer material layer located in the opening of the first photoresist layer; depositing a mandrel material layer after removing the spacer material layer and polishing the mandrel material layer to form a polished mandrel material layer; depositing a second photoresist layer on the polished mandrel material layer and patterning a second opening in the photoresist mask layer to expose an unprotected area of the polished mandrel material layer; removing the polished mandrel material layer located in the unprotected area to form a mandrel; depositing a sidewall spacer layer on the mandrel comprising a remaining mandrel material layer; etching the remaining mandrel material layer; and removing the alignment portion of the spacer material to form the alignment feature and forming the sidewall features in the silicon nitride layer, the silicon dioxide layer, and the hard mask planarization layer.

Yet, according to another embodiment, an integrated circuit component comprises a gate electrode layer; and a hard mask layer on the gate electrode layer; wherein the hard mask layer comprises an alignment feature and a sidewall feature.

BRIEF DESCRIPTION OF THE DRAWINGS

Refer now to the figures, which are exemplary embodiments, and wherein the like elements are numbered alike.

FIGS. 1-10 illustrate an embodiment of a method of preparing an integrated circuit component.

FIG. 1 is a perspective view of an integrated circuit component having a spacer material layer deposited thereon;

FIG. 2 is a perspective view of an integrated circuit component having a patterned mask layer formed thereon;

FIG. 3 is a perspective view of an integrated circuit component having an opening in the spacer material layer;

FIG. 4 is a perspective view of an integrated circuit component having a mandrel material layer deposited thereon;

FIG. 5 is a perspective view of an integrated circuit component having a polished mandrel material layer;

FIG. 6 is a perspective view of an integrated circuit component having a second patterned mask layer formed thereon;

FIG. 7 is a perspective view of an integrated circuit component having an unprotected portion of the mandrel material layer removed;

FIG. 8 is a perspective view of an integrated circuit component having a sidewall spacer layer deposited thereon;

FIG. 9 is a perspective view of an integrated circuit component having the remaining mandrel material layer removed;

FIG. 10 is a perspective view of an integrated circuit component having an alignment feature and formed sidewall features; and

FIG. 11 is an illustration of an embodiment of a method of forming an alignment feature.

DETAILED DESCRIPTION

Structures printed using the current sidewall image transfer (SIT) patterning techniques have a critical dimension that is dictated by the thickness of a sidewall material that is deposited on top of a patterned mandrel. Therefore, for sidewall image transfer based structures that are used for mask alignment, the resulting alignment lines have the same dimension and critical dimension. The alignment lines can therefore be on the order of 10 to 20 nanometers. Unfortunately, this length scale is often too small to be seen by alignment tools, thus often hindering alignment.

The inventors hereof have developed a method of enabling the formation of an alignment feature having a significantly larger length scale than a formed sidewall feature. For example, the alignment feature can have a width on the micrometer length scale as compared to a sidewall feature that can have a width on the nanometer length scale. This method allows for a better overlay and alignment of successive patterned layers.

FIGS. 1-10 illustrate the fabrication of an integrated circuit component in accordance with embodiments of the present disclosure. The fabrication of the integrated circuit component can be started with the component as illustrated in FIG. 1, which can comprise gate electrode layer 2, a hard mask layer located on top of the gate electrode layer, and spacer material layer 10 located on top of the hard mask layer. The hard mask layer can comprise memory layer 4 located on top of gate electrode layer 2, oxide layer 6 located on top of memory layer 4, and hard mask planarization layer 8 located on top of oxide layer 6. Gate electrode layer 2 can be formed on a substrate, which is not shown here for simplicity. Gate electrode layer 2 can comprise a polysilicon.

The substrate can comprise Si (silicon), strained Si, SiC (silicon carbide), Ge (germanium), SiGe (silicon germanium), SiGeC (silicon-germanium-carbon), Si alloys, Ge alloys, GaAs (gallium arsenide), InAs (indium arsenide), InP (indium phosphide), or any combination thereof. The substrate can comprise a semiconductor-on-insulator (SOI) substrate with buried oxide (BOX) layers. The buried oxide layer is an oxide, for example, silicon dioxide, or a nitride, for example, silicon nitride.

The substrate can have a thickness of 0.1 to 750 micrometers. The substrate can comprise bulk Si and can have a thickness of 700 to 800 micrometers. The substrate can comprise a semiconductor-on-insulator (SOI) (such as a silicon-on-insulator) and can have a thickness of 5 to 100 nanometers.

One or both of memory layer 4 and oxide layer 6 can comprise a dielectric material, for example, an oxide, an oxide precursor, or a nitride. Non-limiting examples of materials for forming memory layer 4 and oxide layer 6 include silicon dioxide, silicon nitride, tetraethylorthosilicate (TEOS) oxide, high aspect ratio plasma (HARP) oxide, high temperature oxide (HTO), high density plasma (HDP) oxide, or any combination thereof.

Memory layer 4 and oxide layer 6 can comprise the same or different material(s). For example, memory layer 4 and oxide layer 6 can comprise silicon nitride. Conversely, only memory layer 4 can comprise a silicon nitride and oxide layer 6 can comprise a material other than a silicon nitride. Oxide layer 6 can comprise silicon dioxide (SiO₂), tetraethylorthosilicate (TEOS) oxide, high aspect ratio plasma (HARP) oxide, silicon oxide, high temperature oxide (HTO), high density plasma (HDP) oxide, oxides formed by an atomic layer deposition (ALD) process, or a combination comprising at least one of the foregoing. Oxide layer 6 can comprise silicon dioxide (SiO₂).

One or both of memory layer 4 and oxide layer 6 can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced CVD (PECVD), atomic layer deposition (ALD), evaporation, chemical solution deposition, and/or other like processes.

One or both of memory layer 4 and oxide layer 6 can have a thicknesses of 10 to 200 nanometers, specifically, 20 to 100 nanometers.

Spacer material layer 10 can comprise can comprise an inorganic material such as silicon dioxide, silicon nitride, and the like. Spacer material layer 10 can be formed by atomic layer deposition.

Next, with reference to FIG. 2, mask layer 14 can form a block mask on top of spacer material layer 10 such that an area, where frequency doubling is not desired, can be preserved. This area, also referred to herein as an alignment portion, corresponds to alignment feature 50 as illustrated in FIG. 10. Organic planarizing layer 12 can be located in between spacer material layer 10 and mask layer 14.

Mask layer 14 can be any suitable resist. Suitable resists include photoresists, electron-beam resists, ion-beam resists, X-ray resists, and etchant resists. The resist can comprise a polymeric material, for example, that can be applied by spin casting. The mask may be removed by, for example, an ashing process.

Mask layer 14 can be formed by spin coating a photo resist material followed by photolithography to form one or more of opening(s) 30.

FIG. 3 illustrates that a portion of the spacer material layer 10 can be removed to form one or more of opening(s) 30 corresponding to the opening(s) in mask layer 14. Opening(s) 30 in spacer material layer 10 can be formed by a direction etching process, such as reactive ion etching (RIE), a remote plasma, diluted HF, or chemical vapor/sublimation. Non-limiting examples of suitable etching processes include silicon etching methods selective to oxides. As used herein, the reactive ion etching can comprise a simultaneous exposure to hydrogen (H₂), nitrogen trifluoride (NF₃), and ammonia (NH₃) plasma by-products (SiCoNi process).

Mask layer 14 can be removed, for example, using a solvent or an aqueous developer, for example, using N-methyl-2-pyrrolidone (NMP), toluene, propylene glycol methyl ether acetate (PGMEA), tetramethylammonium hydroxide (TMAH), or a combination comprising at least one of the foregoing.

Next, with reference to FIGS. 4 and 5, mandrel material layer 16 can be deposited on the integrated circuit component (FIG. 4). Mandrel material layer 16 can be located on spacer material layer 10 and an exposed hard mask layer. Mandrel material layer 16 can comprise a polymer, for example, a random copolymer comprising repeat units derived from styrene, methylmethacrylate, or a combination comprising at least one of the foregoing. Mandrel material layer 16 can comprise an inorganic material such as silicon dioxide, silicon nitride, and the like. Mandrel material layer 16 can be formed by spin coating.

Mandrel material layer 16 can then be polished (also referred to as planarized), for example, by chemical and mechanical polishing, to remove the mandrel material that is located on top of spacer material layer 10 to form a flat surface with spacer material layer 10 as illustrated in FIG. 5. For example, mandrel material layer 16 can have the same height (on the z-axis as illustrated in FIG. 1) as spacer material layer 10.

Next, with reference to FIG. 6, lithographic feature(s) 32 can be formed on top of mandrel material layer 16. Lithographic feature(s) 32 can be formed by first applying a mask material followed by forming the features. For example, the mask material can comprise a resist such as a photoresist and the features can be formed by photolithography. Adhesion layer 18 can be formed on top of mandrel material layer 16 prior to applying the mask material.

Lithographic feature(s) 32 can mask an area of mandrel material layer 16 to protect it during a subsequent etching step, where an unprotected area of mandrel material layer 16 that does not have a lithographic feature(s) 32 on top of it, can be subsequently etched.

Second mask layer 114 can be any suitable resist. Suitable resists include photoresists, electron-beam resists, ion-beam resists, X-ray resists, and etchant resists. The resist can comprise a polymeric material, for example, that can be applied by spin casting. The mask may be removed by, for example, an ashing process.

FIG. 7 illustrates that the unprotected portion of spacer material layer 10 can be removed to form one or more mandrels and one or more of mandrel opening(s) 34 corresponding to the space in mandrel material layer 16 that was not covered by second mask layer 114. Mandrel opening(s) 34 in spacer material layer 10 can be formed by a directional etching process, such as reactive ion etching, a remote plasma, diluted hydrogen fluoride, or chemical vapor/sublimation. Non-limiting examples of suitable etching processes include silicon etching methods selective to oxides.

Mandrel opening(s) 34 can have an opening width, w_(m). For example, the opening width, w_(m), can be greater than or equal to 5 nanometers, for example, 5 to 100 nanometers.

Mask layer 114 can be removed, for example, using a solvent or an aqueous developer, for example, using N-methyl-2-pyrrolidone (NMP), toluene, propylene glycol methyl ether acetate (PGMEA), tetramethylammonium hydroxide (TMAH), or a combination comprising at least one of the foregoing.

Next, with reference to FIG. 8, sidewall spacer layer 20 can be deposited onto the top surface of the integrated circuit component. Sidewall spacer layer 20 can form a layer on the sidewalls of mandrel material layer 16 to form sidewall opening(s) 36 that has a sidewall opening width, w_(s), that is less than w_(m). For example, the sidewall opening width can be equal to the opening width minus two times the width of the deposited sidewalls, w_(w), (w_(s)=w_(m)−2w_(w)). The deposited sidewalls can have a width of 5 to 100 nanometers, specifically, 10 to 100 nanometers, more specifically, 10 to 40 nanometers. As is used herein, the width refers to the length in the x-direction as is illustrated in FIG. 1.

Next, with reference to FIG. 9, an anisotropic, top to bottom etching process, such as reactive ion etching, a remote plasma, diluted hydrogen fluoride (such as hydrogen fluoride diluted with ethylene glycol (HFEG)), or chemical vapor/sublimation, can be performed to expose the remaining mandrel material layer 16 by first removing the sidewall spacer layer 20 and any adhesion layer 18 located on top of mandrel material layer 16. Following the etching, the remaining mandrel material layer 16 can be removed. Etching of the sidewall spacer layer 20 and the mandrel material layer 16 can be performed in a single step, for example, if the mandrel material layer 16 comprises a carbon based material; or in multiple etching steps, for example, if the mandrel material layer 16 comprises an inorganic material such as silicon nitride. FIG. 9 illustrates that after removal of the remaining mandrel material layer, the surface comprises spacer etch opening(s) 38 located in the spaces where the mandrel material layer had been.

Finally, FIG. 10 illustrates that a hard mask open can be used to remove the remaining spacer material layer 10 forming alignment feature 50 and to form sidewall feature(s) 52 in the hard mask layer, for example, in memory layer 4, oxide layer 6, and hard mask planarization layer 8, with etched opening(s) 40 located in between sidewall feature(s) 52. The hard mask open can comprise a selective etch process such as a wet etch process. The wet etch process can comprise etching with hydrogen fluoride diluted with ethylene glycol (HFEG).

The width of sidewall feature(s) 52 can correspond to the width of the deposited sidewalls. For example, the sidewall feature(s) 52 can have a width of 5 to 100 nanometers, specifically, 10 to 100 nanometers, more specifically, 10 to 40 nanometers.

The alignment feature can have a width of greater than or equal to 25 nanometers, specifically, 25 to 100 nanometers.

Using the present method, the critical dimension (CD) of the formed integrated circuit component is the thickness of the minimum thickness of sidewall spacer layer 20 that can be deposited. As used herein, the CD refers to a smallest dimension of geometrical features (width of interconnect line, contacts, trenches, etc.), which can be practically formed without any deformation or distortion during semiconductor device/circuit manufacturing.

FIG. 11 is an illustration of an embodiment of a method of forming an alignment feature. Step I comprises depositing a spacer material layer on an integrated circuit component comprising a gate electrode layer and a hard mask layer on the gate electrode layer. The hard mask layer can comprise a memory layer located on top of the gate electrode layer, an oxide layer located on top of the memory layer, and a hard mask planarization layer located on top of the oxide layer.

Step II comprises depositing a first mask layer on the spacer material layer and patterning an opening in the first mask layer. The first mask layer can be located on the alignment portion of the spacer material layer. Step III comprises removing the spacer material layer located in the opening of the first mask layer. Step IV comprises depositing a mandrel material layer after removing the spacer material layer and polishing the mandrel material layer to form a polished mandrel material layer.

Step V comprises depositing a second mask layer on the polished mandrel material layer and patterning a second opening in the second mask layer to expose an unprotected area of the polished mandrel material layer. Step VI comprises removing the polished mandrel material layer located in the unprotected area to form a mandrel. The removing the polished mandrel material layer can comprise reactive ion etching. Step VII comprises depositing a sidewall spacer layer on the mandrel comprising a remaining mandrel material layer. Step VIII comprises etching the remaining mandrel material layer. Step IX comprises removing the alignment portion of the spacer material to form the alignment feature and forming the sidewall features in the hard mask layer.

The following definitions and abbreviations are to be used for the interpretation of the claims and the specification. As used herein, the terms “comprises,” “comprising,” “includes,” “including,” “has,” “having,” “contains” or “containing,” or any other variation thereof, are intended to cover a non-exclusive inclusion. For example, a composition, a mixture, process, method, article, or apparatus that comprises a list of elements is not necessarily limited to only those elements but can include other elements not expressly listed or inherent to such composition, mixture, process, method, article, or apparatus.

As used herein, the articles “a” and “an” preceding an element or component are intended to be nonrestrictive regarding the number of instances (i.e., occurrences) of the element or component. Therefore, “a” or “an” should be read to include one or at least one, and the singular word form of the element or component also includes the plural unless the number is obviously meant to be singular. “or” means “and/or”.

The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present disclosure has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiment was chosen and described in order to best explain the principles of the disclosure and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.

The diagrams depicted herein are just one example. There may be many variations to this diagram or the steps (or operations) described therein without departing from the spirit of the invention. For instance, the steps may be performed in a differing order or steps may be added, deleted or modified. All of these variations are considered a part of this disclosure.

The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

It will also be understood that when an element, such as a layer, region, or substrate is referred to as being “on” or “over” another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or “directly over” another element, there are no intervening elements present.

The descriptions of the various embodiments of the present disclosure have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein. 

1. An integrated circuit component comprising: a gate electrode layer; and a hard mask layer on the gate electrode layer; wherein the hard mask layer is patterned with an alignment feature and a sidewall feature comprising a critical dimension; wherein a width of the alignment feature is greater than the critical dimension; and wherein the critical dimension is less than or equal to about 100 nanometers.
 2. The integrated circuit component of claim 1, wherein the sidewall feature has a width of 5 to 100 nanometers.
 3. The integrated circuit component of claim 1, wherein the sidewall feature has a width of 10 to 100 nanometers.
 4. The integrated circuit component of claim 1, wherein the sidewall feature has a width of 10 to 40 nanometers.
 5. The integrated circuit component of claim 1, wherein the alignment feature has a width of greater than or equal to 1 micrometer.
 6. The integrated circuit component of claim 1, wherein the alignment feature has a width of greater than or equal to 25 nanometers.
 7. The integrated circuit component of claim 1, wherein the alignment feature has a width of 25 to 100 nanometers.
 8. The integrated circuit component of claim 1, wherein the hard layer mask comprises a memory layer located on top of the gate electrode layer, an oxide layer located on top of the memory layer, and a hard mask planarization layer located on top of the oxide layer.
 9. The integrated circuit component of claim 8, wherein the memory layer comprises a dielectric material comprising an oxide, an oxide precursor, or a nitride.
 10. The integrated circuit component of claim 8, wherein the memory layer comprises a silicon nitride.
 11. The integrated circuit component of claim 8, wherein the oxide layer comprises silicon dioxide.
 12. The integrated circuit component of claim 8, wherein the oxide layer has a thickness of 10 to 200 nanometers.
 13. The integrated circuit component of claim 8, wherein the memory layer has a thickness of 10 to 200 nanometers.
 14. The integrated circuit component of claim 8, wherein one or both of the memory layer and the oxide layer has a thickness of 20 to 100 nanometers.
 15. The integrated circuit component of claim 1, wherein the gate electrode layer comprises a polysilicon.
 16. An integrated circuit component comprising: a gate electrode layer; and a hard mask layer on the gate electrode layer; wherein the hard mask layer comprises: a memory layer located on top of the gate electrode layer; an oxide layer located on top of the memory layer; and a hard mask planarization layer located on top of the oxide layer; wherein the hard mask layer comprises an alignment feature and a sidewall feature having a width of 5 to 100 nanometers; wherein a width of the alignment feature is greater than the width of the sidewall feature.
 17. The integrated circuit component of claim 16, wherein the sidewall feature has a width of 10 to 100 nanometers.
 18. The integrated circuit component of claim 16, wherein the alignment feature has a width of greater than or equal to 25 nanometers.
 19. The integrated circuit component of claim 16, wherein the oxide layer comprises silicon dioxide, the memory layer comprises a silicon nitride, and the gate electrode layer comprises a polysilicon.
 20. An integrated circuit component comprising: a polysilicon layer; and a hard mask layer on the polysilicon layer; wherein the hard mask layer comprises: a silicon nitride layer having a nitride layer a thickness of 10 to 200 nanometers located on top of the gate electrode layer; a silicon dioxide layer having an oxide layer thickness of 10 to 200 nanometers located on top of the memory layer; and a hard mask planarization layer located on top of the silicon dioxide layer; wherein the hard mask layer comprises an alignment feature spanning the thickness of the hard mask layer having a width of greater than or equal to 1 micrometer and a sidewall feature spanning the thickness of the hard mask layer having a width of 5 to 100 nanometers. 